1. Field of the Invention
The present invention relates to a circuit testing method. More particularly, the present invention relates to a built-in self-test (BIST) circuit and a testing method thereof.
2. Description of the Related Art
To guarantee the correct operation of a system (for example, an integrated circuit), various methods and tools are set up to test the circuits within the system. Built-in self-test (BIST) is particularly suitable for testing the important circuits (for example, the memory) in a system.
A built-in self-test (BIST) circuit serves the system to self test a specific test circuit in the system (normally for testing the memory of an integrated circuit, called circuit-under-test hereafter). FIG. 1 is a block diagram showing a conventional integrated circuit having a built-in self-test circuit therein. In FIG. 1, the memory 110 represents the circuit-under-test and the address terminal ADDR and the chip select terminal CS represent the plurality of input terminals of the memory 110. Furthermore, the unit circuit (for example, the multiplexer 121 and the OR gate 122) coupled to the memory 110 represents the logic circuit 120 of the system.
Under normal operation, the logic circuit 120 of the integrated circuit will include a plurality of data-signal paths (e.g. address path and data path, address path A, B and C are used as examples) and control-signal lines (e.g. write-enable line and chip-select line, the chip-select line CS1 and CS2 are used as examples) for accessing the memory 110. To facilitate explanation, only the input terminal ADDR of the address bus and the input terminal CS of chip select are used as examples. The multiplexer 121 is used for switching one of the data-signal paths (A, B or C) to the address terminal ADDR of the memory 110. Furthermore, an OR gate 122 connects with different chip-select lines CS1 and CS2 to output one of the input signals to the chip select terminal CS of the memory 110.
In general, an extra multiplexer 132 or an OR gate 133 must be inserted between the logic circuit 120 and the input terminals (for example, the address bus terminal, the data input bus terminal, the chip select terminal and the write enable terminal) of the memory 110 when adding any memory built-in self-test (BIST) circuit 130. When the system operates in a test mode, the BIST controller 131 controls the multiplexer 132 to switch address signal source of the memory 110 from the address signal 123 outputted from the logic circuit 120 to the address signal BISTA outputted from the BIST controller 131. At this moment, the BIST controller 131 generates and outputs a plurality of test data to the memory 110 and then read the output data from the memory 110 to test if the memory 110 operates correctly.
However, in many design, the address bus, chip select lines and write enable lines are timing-critical paths. Hence, the conventional method of adding a BIST circuit for testing the memory often leads to a drop of the clock speed. Therefore, this type of design is unsuitable for a high-speed circuit.